The present invention relates to the field of data processing and more particularly to a device for converting parallel data into serial data, that is, a serializer, or for converting serial data into parallel data, that is, a deserializer.
FIG. 1 schematically and symbolically shows a serializer/deserializer for 8-bit data words. This figure also shows registers arranged according to a matrix, each register being designated by the couple ij of its row number and column number. Thus, the first row comprises registers 00-07; and the last row comprises registers 70-77. In this figure, arrows designate controlled switches. The arrows drawn in solid lines designate switches switched on during a first operation cycle, and the arrows drawn in dashed lines or light grey lines designate switches switched on during a second operation cycle.
The registers of the first column (column 0) and registers of the last row (row 7) are coupled to input terminals E0-E7. The registers of the first row (00-07) and of the last column (07-77) are coupled to output terminals S0-S7.
In FIG. 1, an elementary matrix cell is surrounded by dashed lines around register 54 and this cell is represented in FIGS. 2 and 2A. Register 54 is a one-bit register comprising an input E and an output S and is actuated according to the rate of a clock signal CLK of the circuit. Input E is connected to the left adjacent cell through a first switch SW1 actuated by a singal Q* (complement of signal Q) and to the lower adjacent cell through a second switch SW2 actuated by signal Q. The output S of register 54 is connected to the adjacent cell of the upper row, that is, it is connected to register 44 through associated switch SW2, and to the right-hand cell of the same row, that is, the output is connected to switch SW1 of register 55.
The operation of the circuit of FIG. 1 as a serializer will first be explained. It is assumed that, initially, all registers are empty and that all switches SW1 (arrows drawn in light grey lines) are conductive while all switches SW2 are switched off. Successive data words arrive in parallel at the rate of clock CLK. These words move horizontally from one register to another in the matrix. Thus, after 8 clock pulses, the first word input occupies cells 07-77 of the last column, the second word occupies cells 06-76 of the penultimate column, . . . and the eighth word occupies cells 00-70 of the first column.
Then, at the end of eight cycles, the state of switches SW1 and SW2 is reversed, registers continue to be actuated, and data words continue to be input at the rate of clock CLK. The bits contained in each cell will then be vertically shifted. Thus, on outputs S0 to S7 the eight words input in the matix will appear in serial. While the first bits of these words are output from the first row registers (upper row), the next data word on inputs E0-E7 will enter the last row (lower row).
By repeating this operation, that is, by switching the matrix switches every eight clock pulses, serial words are sequentially obtained on outputs S0-S7 while the words arranged in parallel are input at inputs E0-E7, without interrupting the sequence.
It will be noted that the above described serializer operates as a deserializer without any modification, neither in its structure nor in its control mode. In fact, if 8 serial words arrive on inputs E0-E7, These words are converted to parallel on outputs S0-S7.
A drawback of the device illustrated in FIG. 1 comprising a square matrix structure is that significant space is occupied by the existing connections between the inputs and registers of the last row and first column and between the outputs and registers of the first and last column.
In practice, using CMOS technology wherein the minimum length of a transistor gate is 1.2 .mu.m an 8.times.8 matrix having an elementary cell such as illustrated in FIG. 2 will occupy a surface of about 0.2 mm.sup.2. In this technology, it is not possible to over-miniaturize the dimensions of the connection metallizations, and these connections will occupy a surface of about 0.13 mm.sup.2, which is far from negligible as compared with the surface of the active components of the device.